This invention relates generally to semiconductor devices and, more specifically, to a semiconductor device with a shallow trench collector contact region and a method of manufacturing the same.
In advanced bipolar and BiCMOS technologies, electrical contact to buried layers plays a key role in the performance of the technology. A sinker contact is generally required to reduce the resistance of the collector contact. In a standard process integration sequence, collector sinkers are realized by using high-energy ion implantation of p-type or n-type dopants into the collector epitaxy. Dopant activation and diffusion are then realized by a thermal step (furnace or rapid thermal anneal). The diffusion penetrates into the collector epitaxial layer to contact the underlying buried layer.
To accomplish this, one or two lithographic steps are necessary to selectively introduce dopants into the collector epitaxy. Moreover, high-energy high-dose ion implant capability is used for higher voltage applications in which thick collector epitaxy is used to guarantee high breakdown characteristics.
This can lead to a bottleneck in manufacturing since the total time required to achieve the proper dose at these energies is limited by the equipment and thus slows down the processing of wafers. Furthermore, high energy implants require significantly thicker photoresist masks which make it more difficult to control critical dimensions during implants. It is also possible that some of the high energy implants can reach through the photoresist and potentially contaminate critical devices or structures.
The present invention provides a semiconductor device and method for manufacturing the same that substantially eliminates or reduces at least some of the disadvantages and problems associated with the previously developed semiconductor devices and methods for manufacturing the same.
In accordance with a particular embodiment of the present invention, a method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. At least part of the active region is removed to form a shallow trench opening. A dielectric layer is formed proximate the active region at least partially within the shallow trench opening. At least part of the dielectric layer is removed to form a collector contact region. A collector contact may be formed at the collector contact region. The collector contact may be operable to electrically contact the buried layer.
In accordance with another embodiment, a semiconductor device includes a buried layer of a semiconductor substrate. An active region is adjacent at least a portion of the buried layer. A shallow trench isolation structure is adjacent at least a portion of the active region. A collector contact region is adjacent at least a portion of the shallow trench isolation structure. The collector contact region has a depth approximately equal to a depth of the shallow trench isolation structure. The semiconductor device may include a collector contact formed at the collector contact region. The collector contact may be operable to electrically contact the buried layer.
Technical advantages of particular embodiments of the present invention include a method of manufacturing a semiconductor device utilizing shallow trench isolation to make an electrical contact with a buried layer. Such a method requires less lithographic steps to complete the manufacturing process since separate sinker masks are not needed to electrically contact the buried layer. Accordingly, the total time it takes to manufacture the semiconductor device and the labor resources and costs required are reduced.
Another technical advantage of particular embodiments of the present invention includes a method of manufacturing a semiconductor device that does not require high energy ion implantation to make the contact between a collector and the buried layer since the collector can be formed within a shallow trench and therefore closer in proximity to the buried layer. This can reduce the amount of time it takes to manufacture semiconductor device. It can also decrease the potential for contamination of critical devices or structures since the use of high energy implants can lead to such contamination during the manufacturing process.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions and claims. Moreover, while specific advantages have been enumerated above, various embodiments may include all, some or none of the enumerated advantages.